1. Field of the Invention
The present invention relates generally to integrated circuits and more particularly to efficient block data transfers over a serial test port.
2. Discussion of the Related Art
Complex integrated circuits have become increasingly difficult to test. One mechanism for testing these complex integrated circuits uses a Joint Test Action Group (“JTAG”) test access port (“TAP”) as defined in IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture (the “IEEE Standard”), which is incorporated herein by reference in its entirety for all purposes. The JTAG TAP provides an external interface to the integrated circuit whereby the integrated circuit can be debugged. According to the standard, a TAP is added to each integrated circuit. The TAP includes at least three inputs: a test clock (“TCLK”), a test mode select (“TMS”), and a test data in (“TDI”) port. The TAP includes at least one output: a test data out (“TDO”) port. Data is serially shifted from the TDI port and into the integrated circuit and serially shifted out of the integrated circuit and onto the TDO port. In this manner, “test vectors” may be written to or read from the integrated circuit via a test probe to determine whether the integrated circuit is operating properly.
Software debug on complex integrated circuits has likewise become increasingly difficult to conduct. In this regard, an extension of the JTAG standard, referred to as EJTAG, has been developed. EJTAG is a hardware/software subsystem that provides comprehensive debugging and performance tuning capabilities to processors and to system-on-chip components having processor cores. EJTAG exploits the infrastructure provided by the JTAG Test Access Port (TAP) standard to provide an external interface, and extends an instruction set of the processor and privileged resource architectures to provide a standard software architecture for integrated system debugging.
Using EJTAG, instructions to be executed by the processor, in addition to data, may be downloaded to the processor via the test probe. Serially downloading instructions, which are executed as they are received by the processor, causes the processor to operate particularly slowly. One conventional mechanism to speed up this process is to download all the instructions to be executed by the processor to some portion of the processor's memory upon entering debug mode.
As serially shifting instructions and data to and from a processor through EJTAG is extremely time consuming relative to the operational speeds of the processor, existing EJTAG protocols (specifically, versions 2.5 and earlier) may require as many as 149 overhead test clock (“TCK”) cycles for every 32 bits of instruction or data transferred. Accordingly, even at reasonable rates for TCK, transferring large blocks of instructions or data to and from the integrated circuit is often measured in terms of minutes.
What is needed therefore is a system and method for improving efficiency of block data transfer operations to and from a processor implementing EJTAG.